MSc thesis project proposal

[2022] Charge-Sampling Fractional-N PLL (SiTime)

Project outside the university



A divider-less sub-sampling PLL (SSPLL) based on voltage sampling can achieve low jitter while dissipating low power, as it eliminates the noise of the feedback divider and suppresses the noise of the CP and phase detector thanks to its high phase-detection gain (KPD). Unfortunately, the direct sampling of the voltage-controlled oscillator (VCO) voltage by a low-frequency reference clock (REF) can introduce a high SREF due to the periodic tank-capacitance perturbation, reference clock feedthrough, and charge injection from the sampling switch to the VCO. In [1-2], we introduced a charge-sampling PLL (CSPLL), whose phase-detection mechanism is based on windowed integration of the RF current. The proposed phase detector also dramatically reduces reference spurs even without power-hungry isolation buffers by both minimizing the modulated capacitance seen by the VCO tank and reducing the duty cycle of the sampling clock. Inaddition, it also offers a high-phase detection gain even without requiring an RF bandwidth at the sampler output, leading to a low power, and a negligible phase noise contribution from the PLL loop components. Measurement results show that the CSPLL achieves 48.6-fs RMS jitter and −77.3-dBc reference spur at an 11.2-GHz carrier frequency while consuming 5 mW. This corresponds to the best-reported jitter-power FOM and reference spur performance. 

Towards Fractional-N Operation

Our current CSPLL generates ultra-low-jitter tone at integer-N channels. However, it cannot be used for synthesizing the fractional-N channels where the quantization error (Qerr) between the reference frequency (fREF), and the VCO frequency (fVCO) makes sampling points fall outside the linear range of the charge sampling phase detector. This project aims to modify the current CS-PLL structure to synthesize fractional frequencies while maintaining its state-of-the-art FOM. It is generally to add a digital-to-time converter (DTC) between the reference buffer and the phase detector to cancel the Qerr at the fractional-N channels, thus locking the PLL to the desired frequency. However, in this approach, the DTC is located before the sub-sampling phase detector. Hence, its thermal noise cannot be suppressed with the high phase-detection gain (KPD) of the phase detector, thus severely degrading the PLL in-band phase noise. In this project, we will investigate to remove Qerr by adding a current-steering digital-to-analog converter (DAC) at the output of the phase detector. In this way, the thermal noise of the DAC is greatly suppressed by KPD, improving the PLL in-band phase noise. However, we need to increase the phase detector linear range and deal with KPD variations as Qerr still exists at the phase detector input.

Useful Information

This project is with collaboration with SiTime Corporation and This project comes with a student stipend!

Sitime Corporation develops silicon-based timing solutions. The Company manufacturers oscillators, clock generators, and embedded resonators used for ethernet switches, computing devices, graphics cards, disk drives, mobile phones, and subscriber identity module cards. Sitime serves customers worldwide. 


[1] J. Gong, E. Charbon, F. Sebastiano and M. Babaie, "A Low-Jitter and Low-Spur Charge-Sampling PLL," in IEEE Journal of Solid-State Circuits, doi: 10.1109/JSSC.2021.3105335.

[2] J. Gong, F. Sebastiano, E. Charbon, M. Babaie, “A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter, -258.9 dB FOM and -65 dBc Reference Spur,” Proc. of IEEE Radio Frequency Integrated Circuits (RFIC) Symp Los Angeles, CA, USA, 2020, pp. 15-18, doi: 10.1109/RFIC49505.2020.9218380.




·      Understanding the requirements of the targeted application

·      Defining PLL specifications and requirements

·      Literature review on sub-sampling PLL and DTC structures

·      Developing Verilog-A model of the PLL

·      Performing system analysis/simulations and finding the optimum structure

·      Simulating the circuit in cadence Finding the related issues Finding novel solutions

·      Circuit design in TSMC 40-nm CMOS 

·      Layout of test chip and Post layout simulations

·      Tape-out 

·      Preparing measurement setup

·      Measurement and analyzing the measured performance of the chip

·      Writing the thesis

·      Publishing a paper


dr. Masoud Babaie

Electronic Circuits and Architectures Group

Department of Microelectronics

Last modified: 2022-03-11